
/**
 * DO NOT MODIFY THIS FILE!
 *
 * In Verilator, use the behavioral model.
 * Otherwise XPM_MEMORY_SPRAM will be used.
 *
 * Default configuration: 64 bytes / byte-write enabled
 */
 // $clog2(x): y = log_2^x

module LUTRAM #(
    parameter BYTE_WIDTH = 8,
    parameter WORD_WIDTH = 32,
    parameter BYTE_WRITE = 0,

	parameter INIT_FILE = "none",
	parameter INIT_PARAM = "0",
	parameter WRITE_MODE = "read_first",
	parameter READ_LATENCY = 0,

    parameter DEPTH = 8,
    parameter ADDR_WIDTH = 3,
    parameter LINE_WIDTH = BYTE_WRITE ? BYTE_WIDTH : WORD_WIDTH,
    parameter NUM_BITS   = DEPTH * WORD_WIDTH
) (
    input 								clk,
	input  								en,

    input  [ADDR_WIDTH-1: 0]   			addr,
    input [WORD_WIDTH/LINE_WIDTH-1: 0]	we,
    input  [WORD_WIDTH-1: 0]   			wdata,
    output [WORD_WIDTH-1: 0]   			rdata
);

    xpm_memory_spram #(
        .ADDR_WIDTH_A(ADDR_WIDTH),
        .AUTO_SLEEP_TIME(0),
        .BYTE_WRITE_WIDTH_A(LINE_WIDTH),
        .CASCADE_HEIGHT(0),
        .ECC_MODE("no_ecc"),
        .MEMORY_INIT_FILE(INIT_FILE),
        .MEMORY_INIT_PARAM(INIT_PARAM),
        .MEMORY_OPTIMIZATION("true"),
        .MEMORY_PRIMITIVE("distributed"),
        .MEMORY_SIZE(NUM_BITS),
        .MESSAGE_CONTROL(0),
        .READ_DATA_WIDTH_A(WORD_WIDTH),
        .READ_LATENCY_A(READ_LATENCY),
        .READ_RESET_VALUE_A("0"),
        .RST_MODE_A("SYNC"),
        .SIM_ASSERT_CHK(1),
        .USE_MEM_INIT(1),
        .WAKEUP_TIME("disable_sleep"),
        .WRITE_DATA_WIDTH_A(WORD_WIDTH),
        .WRITE_MODE_A(WRITE_MODE)
    ) xpm_memory_spram_inst (
        .clka(clk), .ena(en),
        .addra(addr),
        .wea(we),
        .dina(wdata),
        .douta(rdata),

        .regcea(1),
        .rsta(0),
        .sleep(0),
        .injectdbiterra(0),
        .injectsbiterra(0)
    );

endmodule

module TDPRAM #(
	 parameter BYTE_WIDTH = 8,
    parameter WORD_WIDTH = 32,
    parameter BYTE_WRITE = 0,

	parameter INIT_FILE = "none",
	parameter INIT_PARAM = "0",
	parameter WRITE_MODE = "read_first",
	parameter READ_LATENCY = 0,

    parameter DEPTH = 8,
    parameter ADDR_WIDTH = 3,
    parameter LINE_WIDTH = BYTE_WRITE ? BYTE_WIDTH : WORD_WIDTH,
    parameter NUM_BITS   = DEPTH * WORD_WIDTH
)(
    input 								clk,

	input  								ena,
    input  [ADDR_WIDTH-1: 0]   			addra,
    input [WORD_WIDTH/LINE_WIDTH-1: 0]	wea,
    input  [WORD_WIDTH-1: 0]   			dina,
    output [WORD_WIDTH-1: 0]   			douta,

	input  								enb,
    input  [ADDR_WIDTH-1: 0]   			addrb,
    input [WORD_WIDTH/LINE_WIDTH-1: 0]	web,
    input  [WORD_WIDTH-1: 0]   			dinb,
    output [WORD_WIDTH-1: 0]   			doutb
);

   xpm_memory_tdpram #(
      .ADDR_WIDTH_A(ADDR_WIDTH),               // DECIMAL
      .ADDR_WIDTH_B(ADDR_WIDTH),               // DECIMAL
      .AUTO_SLEEP_TIME(0),            // DECIMAL
      .BYTE_WRITE_WIDTH_A(LINE_WIDTH),        // DECIMAL
      .BYTE_WRITE_WIDTH_B(LINE_WIDTH),        // DECIMAL
      .CASCADE_HEIGHT(0),             // DECIMAL
      .CLOCKING_MODE("common_clock"), // String
      .ECC_MODE("no_ecc"),            // String
      .MEMORY_INIT_FILE(INIT_FILE),      // String
      .MEMORY_INIT_PARAM(INIT_PARAM),        // String
      .MEMORY_OPTIMIZATION("true"),   // String
      .MEMORY_PRIMITIVE("distributed"),      // String
      .MEMORY_SIZE(NUM_BITS),             // DECIMAL
      .MESSAGE_CONTROL(0),            // DECIMAL
      .READ_DATA_WIDTH_A(WORD_WIDTH),         // DECIMAL
      .READ_DATA_WIDTH_B(WORD_WIDTH),         // DECIMAL
      .READ_LATENCY_A(READ_LATENCY),             // DECIMAL
      .READ_LATENCY_B(READ_LATENCY),             // DECIMAL
      .READ_RESET_VALUE_A("0"),       // String
      .READ_RESET_VALUE_B("0"),       // String
      .RST_MODE_A("SYNC"),            // String
      .RST_MODE_B("SYNC"),            // String
      .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
      .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL
      .USE_MEM_INIT(1),               // DECIMAL
      .WAKEUP_TIME("disable_sleep"),  // String
      .WRITE_DATA_WIDTH_A(WORD_WIDTH),        // DECIMAL
      .WRITE_DATA_WIDTH_B(WORD_WIDTH),        // DECIMAL
      .WRITE_MODE_A("read_first"),     // String
      .WRITE_MODE_B(WRITE_MODE)      // String
   )
   xpm_memory_tdpram_inst (

      .douta(douta),                   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
      .doutb(doutb),                   // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
      .sbiterra(sbiterra),             // 1-bit output: Status signal to indicate single bit error occurrence
                                       // on the data output of port A.

      .sbiterrb(sbiterrb),             // 1-bit output: Status signal to indicate single bit error occurrence
                                       // on the data output of port B.

      .addra(addra),                   // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
      .addrb(addrb),                   // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
      .clka(clk),                     // 1-bit input: Clock signal for port A. Also clocks port B when
                                       // parameter CLOCKING_MODE is "common_clock".

      .clkb(clk),                     // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
                                       // "independent_clock". Unused when parameter CLOCKING_MODE is
                                       // "common_clock".

      .dina(dina),                     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
      .dinb(dinb),                     // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
      .ena(ena),                       // 1-bit input: Memory enable signal for port A. Must be high on clock
                                       // cycles when read or write operations are initiated. Pipelined
                                       // internally.

      .enb(enb),                       // 1-bit input: Memory enable signal for port B. Must be high on clock
                                       // cycles when read or write operations are initiated. Pipelined
                                       // internally.

      .injectdbiterra(0), // 1-bit input: Controls double bit error injection on input data when
                                       // ECC enabled (Error injection capability is not available in
                                       // "decode_only" mode).

      .injectdbiterrb(0), // 1-bit input: Controls double bit error injection on input data when
                                       // ECC enabled (Error injection capability is not available in
                                       // "decode_only" mode).

      .injectsbiterra(0), // 1-bit input: Controls single bit error injection on input data when
                                       // ECC enabled (Error injection capability is not available in
                                       // "decode_only" mode).

      .injectsbiterrb(0), // 1-bit input: Controls single bit error injection on input data when
                                       // ECC enabled (Error injection capability is not available in
                                       // "decode_only" mode).

      .regcea(1),                 // 1-bit input: Clock Enable for the last register stage on the output
                                       // data path.

      .regceb(1),                 // 1-bit input: Clock Enable for the last register stage on the output
                                       // data path.

      .rsta(0),                     // 1-bit input: Reset signal for the final port A output register stage.
                                       // Synchronously resets output port douta to the value specified by
                                       // parameter READ_RESET_VALUE_A.

      .rstb(0),                     // 1-bit input: Reset signal for the final port B output register stage.
                                       // Synchronously resets output port doutb to the value specified by
                                       // parameter READ_RESET_VALUE_B.

      .sleep(0),                   // 1-bit input: sleep signal to enable the dynamic power saving feature.
      .wea(wea),                       // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                                       // for port A input data port dina. 1 bit wide when word-wide writes are
                                       // used. In byte-wide write configurations, each bit controls the
                                       // writing one byte of dina to address addra. For example, to
                                       // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                       // is 32, wea would be 4'b0010.

      .web(web)                        // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
                                       // for port B input data port dinb. 1 bit wide when word-wide writes are
                                       // used. In byte-wide write configurations, each bit controls the
                                       // writing one byte of dinb to address addrb. For example, to
                                       // synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B
                                       // is 32, web would be 4'b0010.

   );
endmodule

module SPRAM #(
    parameter BYTE_WIDTH = 8,
    parameter WORD_WIDTH = 32,
    parameter BYTE_WRITE = 0,

	parameter INIT_FILE = "none",
	parameter INIT_PARAM = "0",
	parameter WRITE_MODE = "read_first",
	parameter READ_LATENCY = 0,

    parameter DEPTH = 8,
    parameter ADDR_WIDTH = 3,
    parameter LINE_WIDTH = BYTE_WRITE ? BYTE_WIDTH : WORD_WIDTH,
    parameter NUM_BITS   = DEPTH * WORD_WIDTH
) (
    input 								clk,
	input  								en,

    input  [ADDR_WIDTH-1: 0]   			addr,
    input [WORD_WIDTH/LINE_WIDTH-1: 0]	we,
    input  [WORD_WIDTH-1: 0]   			din,
    output [WORD_WIDTH-1: 0]   			dout
);
    wire sbiterra;
	wire dbiterra;
	xpm_memory_spram #(
      .ADDR_WIDTH_A(ADDR_WIDTH),              // DECIMAL
      .AUTO_SLEEP_TIME(0),           // DECIMAL
      .BYTE_WRITE_WIDTH_A(LINE_WIDTH),       // DECIMAL
      .CASCADE_HEIGHT(0),            // DECIMAL
      .ECC_MODE("no_ecc"),           // String
      .MEMORY_INIT_FILE("none"),     // String
      .MEMORY_INIT_PARAM("0"),       // String
      .MEMORY_OPTIMIZATION("true"),  // String
      .MEMORY_PRIMITIVE("auto"),     // String
      .MEMORY_SIZE(NUM_BITS),            // DECIMAL
      .MESSAGE_CONTROL(0),           // DECIMAL
      .READ_DATA_WIDTH_A(WORD_WIDTH),        // DECIMAL
      .READ_LATENCY_A(READ_LATENCY),            // DECIMAL
      .READ_RESET_VALUE_A("0"),      // String
      .RST_MODE_A("SYNC"),           // String
      .SIM_ASSERT_CHK(0),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
      .USE_MEM_INIT(1),              // DECIMAL
      .WAKEUP_TIME("disable_sleep"), // String
      .WRITE_DATA_WIDTH_A(WORD_WIDTH),       // DECIMAL
      .WRITE_MODE_A(WRITE_MODE)    // String
   )
   xpm_memory_spram_inst (

      .douta(dout),                   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.

      .addra(addr),                   // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
      .clka(clk),                     // 1-bit input: Clock signal for port A.
      .dina(din),                     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
      .ena(en),                       // 1-bit input: Memory enable signal for port A. Must be high on clock
                                       // cycles when read or write operations are initiated. Pipelined
                                       // internally.

      .injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
                                       // ECC enabled (Error injection capability is not available in
                                       // "decode_only" mode).

      .injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
                                       // ECC enabled (Error injection capability is not available in
                                       // "decode_only" mode).
                               
 	  .sbiterra(sbiterra),             // 1-bit output: Status signal to indicate single bit error occurrence
                                       // on the data output of port A.

 	  .dbiterra(dbiterra),             // 1-bit output: Status signal to indicate double bit error occurrence
                                       // on the data output of port A.
					
      .regcea(1'b0),                 // 1-bit input: Clock Enable for the last register stage on the output
                                       // data path.

      .rsta(1'b0),                     // 1-bit input: Reset signal for the final port A output register stage.
                                       // Synchronously resets output port douta to the value specified by
                                       // parameter READ_RESET_VALUE_A.

      .sleep(1'b0),                   // 1-bit input: sleep signal to enable the dynamic power saving feature.
      .wea(we)                        // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                                       // for port A input data port dina. 1 bit wide when word-wide writes are
                                       // used. In byte-wide write configurations, each bit controls the
                                       // writing one byte of dina to address addra. For example, to
                                       // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                       // is 32, wea would be 4'b0010.

   );

endmodule

module SDPRAM#(
	parameter BYTE_WIDTH = 8,
    parameter WORD_WIDTH = 32,
    parameter BYTE_WRITE = 0,

	parameter INIT_FILE = "none",
	parameter INIT_PARAM = "0",
	parameter WRITE_MODE = "read_first",
	parameter READ_LATENCY = 0,
	parameter MEMORY_PRIMITIVE = "auto",

    parameter DEPTH = 8,
    parameter ADDR_WIDTH = 3,
    parameter LINE_WIDTH = BYTE_WRITE ? BYTE_WIDTH : WORD_WIDTH,
    parameter NUM_BITS   = DEPTH * WORD_WIDTH
)(
    input 								clk,
	input  								ena,
    input  [ADDR_WIDTH-1: 0]   			addra,
    input [WORD_WIDTH/LINE_WIDTH-1: 0]	wea,
    input  [WORD_WIDTH-1: 0]   			dina,
    output [WORD_WIDTH-1: 0]   			douta,

	input  								enb,
    input  [ADDR_WIDTH-1: 0]   			addrb,
    output [WORD_WIDTH-1: 0]   			doutb
);
 xpm_memory_dpdistram #(
      .ADDR_WIDTH_A(ADDR_WIDTH),               // DECIMAL
      .ADDR_WIDTH_B(ADDR_WIDTH),               // DECIMAL
      .BYTE_WRITE_WIDTH_A(LINE_WIDTH),        // DECIMAL
      .CLOCKING_MODE("common_clock"), // String
      .MEMORY_INIT_FILE(INIT_FILE),      // String
      .MEMORY_INIT_PARAM(INIT_PARAM),        // String
      .MEMORY_OPTIMIZATION("true"),   // String
      .MEMORY_SIZE(NUM_BITS),             // DECIMAL
      .MESSAGE_CONTROL(0),            // DECIMAL
      .READ_DATA_WIDTH_A(WORD_WIDTH),         // DECIMAL
      .READ_DATA_WIDTH_B(WORD_WIDTH),         // DECIMAL
      .READ_LATENCY_A(READ_LATENCY),             // DECIMAL
      .READ_LATENCY_B(READ_LATENCY),             // DECIMAL
      .READ_RESET_VALUE_A("0"),       // String
      .READ_RESET_VALUE_B("0"),       // String
      .RST_MODE_A("SYNC"),            // String
      .RST_MODE_B("SYNC"),            // String
      .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
      .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL
      .USE_MEM_INIT(1),               // DECIMAL
      .WRITE_DATA_WIDTH_A(WORD_WIDTH)         // DECIMAL
   )
   xpm_memory_dpdistram_inst (
      .douta(douta),   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
      .doutb(doutb),   // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
      .addra(addra),   // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
      .addrb(addrb),   // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
      .clka(clk),     // 1-bit input: Clock signal for port A. Also clocks port B when parameter CLOCKING_MODE
                       // is "common_clock".

      .clkb(clk),     // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
                       // "independent_clock". Unused when parameter CLOCKING_MODE is "common_clock".

      .dina(dina),     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
      .ena(ena),       // 1-bit input: Memory enable signal for port A. Must be high on clock cycles when read
                       // or write operations are initiated. Pipelined internally.

      .enb(enb),       // 1-bit input: Memory enable signal for port B. Must be high on clock cycles when read
                       // or write operations are initiated. Pipelined internally.

      .regcea(0), // 1-bit input: Clock Enable for the last register stage on the output data path.
      .regceb(0), // 1-bit input: Do not change from the provided value.
      .rsta(1'b0),     // 1-bit input: Reset signal for the final port A output register stage. Synchronously
                       // resets output port douta to the value specified by parameter READ_RESET_VALUE_A.

      .rstb(1'b0),     // 1-bit input: Reset signal for the final port B output register stage. Synchronously
                       // resets output port doutb to the value specified by parameter READ_RESET_VALUE_B.

      .wea(wea)        // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector for port A input
                       // data port dina. 1 bit wide when word-wide writes are used. In byte-wide write
                       // configurations, each bit controls the writing one byte of dina to address addra. For
                       // example, to synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A is
                       // 32, wea would be 4'b0010.

   );
endmodule

module SyncFifo #(
	parameter WIDTH=32,
	parameter DEPTH=256,
	parameter MEMORY_TYPE="distributed",
	parameter READ_LATENCY=1,
	parameter EMPTY_THRESH=10,
	parameter FULL_THRESH=10,
	parameter DATA_COUNT_WIDTH=$clog2(DEPTH)+1
)(
	input 				clk,
	input 				rst,
	input 				rd_en,
	input 				wr_en,
	input [WIDTH-1: 0] 	din,
	output 				empty,
	output 				full,
	output 				almost_empty,
	output 				almost_full,
	output 				data_valid,
	output [WIDTH-1: 0]	dout	
);
	xpm_fifo_async #(
      .DOUT_RESET_VALUE("0"),    // String
      .ECC_MODE("no_ecc"),       // String
      .FIFO_MEMORY_TYPE(MEMORY_TYPE), // String
      .FIFO_READ_LATENCY(READ_LATENCY),     // DECIMAL
      .FIFO_WRITE_DEPTH(DEPTH),   // DECIMAL
      .FULL_RESET_VALUE(0),      // DECIMAL
      .PROG_EMPTY_THRESH(EMPTY_THRESH),    // DECIMAL
      .PROG_FULL_THRESH(FULL_THRESH),     // DECIMAL
      .RD_DATA_COUNT_WIDTH(DATA_COUNT_WIDTH),   // DECIMAL
      .READ_DATA_WIDTH(WIDTH),      // DECIMAL
      .READ_MODE("std"),         // String
      .SIM_ASSERT_CHK(0),        // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
      .USE_ADV_FEATURES("0707"), // String
      .WAKEUP_TIME(0),           // DECIMAL
      .WRITE_DATA_WIDTH(WIDTH),     // DECIMAL
      .WR_DATA_COUNT_WIDTH(DATA_COUNT_WIDTH)    // DECIMAL
	)
	xpm_fifo_sync_inst (
      .almost_empty(almost_empty),   // 1-bit output: Almost Empty : When asserted, this signal indicates that
                                     // only one more read can be performed before the FIFO goes to empty.

      .almost_full(almost_full),     // 1-bit output: Almost Full: When asserted, this signal indicates that
                                     // only one more write can be performed before the FIFO is full.

      .data_valid(data_valid),       // 1-bit output: Read Data Valid: When asserted, this signal indicates
                                     // that valid data is available on the output bus (dout).


      .dout(dout),                   // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
                                     // when reading the FIFO.

      .empty(empty),                 // 1-bit output: Empty Flag: When asserted, this signal indicates that the
                                     // FIFO is empty. Read requests are ignored when the FIFO is empty,
                                     // initiating a read while empty is not destructive to the FIFO.

      .full(full),                   // 1-bit output: Full Flag: When asserted, this signal indicates that the
                                     // FIFO is full. Write requests are ignored when the FIFO is full,
                                     // initiating a write when the FIFO is full is not destructive to the
                                     // contents of the FIFO.

								
      .din(din),                     // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
                                     // writing the FIFO.

      .injectdbiterr(1'b0), // 1-bit input: Double Bit Error Injection: Injects a double bit error if
                                     // the ECC feature is used on block RAMs or UltraRAM macros.

      .injectsbiterr(1'b0), // 1-bit input: Single Bit Error Injection: Injects a single bit error if
                                     // the ECC feature is used on block RAMs or UltraRAM macros.
      .rd_clk(clk),               // 1-bit input: Read clock: Used for read operation. rd_clk must be a free
                                     // running clock.

      .rd_en(rd_en),                 // 1-bit input: Read Enable: If the FIFO is not empty, asserting this
                                     // signal causes data (on dout) to be read from the FIFO. Must be held
                                     // active-low when rd_rst_busy is active high.

      .rst(1'b0),                     // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
                                     // unstable at the time of applying reset, but reset must be released only
                                     // after the clock(s) is/are stable.

      .sleep(1'b0),                 // 1-bit input: Dynamic power saving- If sleep is High, the memory/fifo
                                     // block is in power saving mode.

      .wr_clk(clk),               // 1-bit input: Write clock: Used for write operation. wr_clk must be a
                                     // free running clock.

      .wr_en(wr_en)                  // 1-bit input: Write Enable: If the FIFO is not full, asserting this
                                     // signal causes data (on din) to be written to the FIFO Must be held
                                     // active-low when rst or wr_rst_busy or rd_rst_busy is active high

	);
endmodule

module BSDPRAM #(
	 parameter BYTE_WIDTH = 8,
    parameter WORD_WIDTH = 32,
    parameter BYTE_WRITE = 0,

	parameter INIT_FILE = "none",
	parameter INIT_PARAM = "0",
	parameter WRITE_MODE = "read_first",
	parameter READ_LATENCY = 0,
	parameter MEMORY_PRIMITIVE = "auto",

    parameter DEPTH = 8,
    parameter ADDR_WIDTH = 3,
    parameter LINE_WIDTH = BYTE_WRITE ? BYTE_WIDTH : WORD_WIDTH,
    parameter NUM_BITS   = DEPTH * WORD_WIDTH
)(
    input 								clk,
	input  								ena,
    input  [ADDR_WIDTH-1: 0]   			addra,
    input [WORD_WIDTH/LINE_WIDTH-1: 0]	wea,
    input  [WORD_WIDTH-1: 0]   			dina,

	input  								enb,
    input  [ADDR_WIDTH-1: 0]   			addrb,
    output [WORD_WIDTH-1: 0]   			doutb
);
   xpm_memory_sdpram #(
      .ADDR_WIDTH_A(ADDR_WIDTH),               // DECIMAL
      .ADDR_WIDTH_B(ADDR_WIDTH),               // DECIMAL
      .AUTO_SLEEP_TIME(0),            // DECIMAL
      .BYTE_WRITE_WIDTH_A(LINE_WIDTH),        // DECIMAL
      .CASCADE_HEIGHT(0),             // DECIMAL
      .CLOCKING_MODE("common_clock"), // String
      .ECC_MODE("no_ecc"),            // String
      .MEMORY_INIT_FILE(INIT_FILE),      // String
      .MEMORY_INIT_PARAM(INIT_PARAM),        // String
      .MEMORY_OPTIMIZATION("true"),   // String
      .MEMORY_PRIMITIVE(MEMORY_PRIMITIVE),      // String
      .MEMORY_SIZE(NUM_BITS),             // DECIMAL
      .MESSAGE_CONTROL(0),            // DECIMAL
      .READ_DATA_WIDTH_B(WORD_WIDTH),         // DECIMAL
      .READ_LATENCY_B(READ_LATENCY),             // DECIMAL
      .READ_RESET_VALUE_B("0"),       // String
      .RST_MODE_A("SYNC"),            // String
      .RST_MODE_B("SYNC"),            // String
      .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
      .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL
      .USE_MEM_INIT(1),               // DECIMAL
      .WAKEUP_TIME("disable_sleep"),  // String
      .WRITE_DATA_WIDTH_A(WORD_WIDTH),        // DECIMAL
      .WRITE_MODE_B(WRITE_MODE)      // String
   )
   xpm_memory_sdpram_inst (
      .doutb(doutb),                   // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.

      .addra(addra),                   // ADDR_WIDTH_A-bit input: Address for port A write operations.
      .addrb(addrb),                   // ADDR_WIDTH_B-bit input: Address for port B read operations.
      .clka(clk),                     // 1-bit input: Clock signal for port A. Also clocks port B when
                                       // parameter CLOCKING_MODE is "common_clock".

      .clkb(clk),                     // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
                                       // "independent_clock". Unused when parameter CLOCKING_MODE is
                                       // "common_clock".

      .dina(dina),                     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
      .ena(ena),                       // 1-bit input: Memory enable signal for port A. Must be high on clock
                                       // cycles when write operations are initiated. Pipelined internally.

      .enb(enb),                       // 1-bit input: Memory enable signal for port B. Must be high on clock
                                       // cycles when read operations are initiated. Pipelined internally.

      .injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
                                       // ECC enabled (Error injection capability is not available in
                                       // "decode_only" mode).

      .injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
                                       // ECC enabled (Error injection capability is not available in
                                       // "decode_only" mode).

      .regceb(1'b0),                 // 1-bit input: Clock Enable for the last register stage on the output
                                       // data path.

      .rstb(1'b0),                     // 1-bit input: Reset signal for the final port B output register stage.
                                       // Synchronously resets output port doutb to the value specified by
                                       // parameter READ_RESET_VALUE_B.

      .sleep(1'b0),                   // 1-bit input: sleep signal to enable the dynamic power saving feature.
      .wea(wea)                        // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                                       // for port A input data port dina. 1 bit wide when word-wide writes are
                                       // used. In byte-wide write configurations, each bit controls the
                                       // writing one byte of dina to address addra. For example, to
                                       // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                       // is 32, wea would be 4'b0010.

   );
endmodule
